Semiconductor device manufacturers are constantly striving to increase the performance of their products, while decreasing their cost of manufacture. A cost intensive area in the manufacture of semiconductor device packages is packaging the semiconductor chip. Thus, semiconductor device packages and methods of manufacturing the same at low expenses and high yield are desirable. In particular, the performance of power semiconductor device packages is dependent from the heat dissipation capability provided by the package. Geometry of the package in terms of package layout, footprint, distribution of terminal etc. may strongly affect the performance of the package. Packaging concepts of power devices providing high thermal robustness at low expenses and increased user benefits in view of application variability are desirable.